The calibration and tuning of system timing provided by a system timing generator circuit is a critical factor in system performance including memory performance. Increasing clock frequencies require less skew between related signals while timing measurement becomes more difficult. Both factory calibration and field tuning may be unsatisfactory for a subsequent user. Inexperienced technicians may also misadjust timing during factory or field tuning.
Failure of system timing is also due to the use of discrete wire wound delay line components packaged in separate dual-in-line packages (DIPs). Such discrete delay lines are unreliable and a major cause of system failure. Other timing calibration tools such as monostable multi-vibrators and decoded counters suffer from drift and low resolution.
The present invention seeks to provide an integrated circuit replacement for discrete delay lines using a programmable and controllable variable timing generator circuit formed directly on the integrated circuit chip device. According to the invention access to the new integrated circuit programmable timing generator circuit is obtained through a standard test access port (TAP) such as the IEEE Standard 1149.1 Test Access Port and Boundary Scan Architecture and the JTAG Version 2.0 Protocol for a Test Access Port. The present invention is therefore applicable to IC devices with a test access port of the type illustrated in FIGS. 1-4.
The test access port (TAP) defined by IEEE Standard 1149.1 Test Access Port and JTAG Version 2.0 for incorporation on an integrated circuit chip is illustrated in FIG. 1. At least four pins of the IC device and up to 3% to 25% of the chip silicon surface area is dedicated to the test access port and associated TAP circuits. The TAP is intended to standardize and facilitate boundary scan testing and other design specific testing of the IC device while the chip is still mounted on a circuit board and without separate test instrumentation. The TAP permits all phases of testing with access at all pins of the IC device through boundary scan principles even for surface mount devices and without the necessity of "bed of nails" physical contact. Access to all pins for testing is achieved electronically through the boundary scan shift register, one of the test data registers of the test access port.
The dedicated pins for the test access port include a test data input (TDI) pin to receive data signals for the test data registers (TDRs) and to receive instruction codes for the test instruction register TIR. The test data output (TDO) pin shifts out data signals from the TDRs and instruction codes from the TIR for example for input to the TDI pin of the next IC device on a circuit board. Data signals and instruction codes are shifted out from the TDRs and TIR to the TDO pin through respective multiplexers MUX, a latch or passgate, and an output buffer coupled to the TDO pin.
The remaining two required pins of the standard TAP are a test mode select (TMS) pin and a test clock (TCK) pin which provide respective control and clock signals to the TAP controller which in turn directs operation of the test access port. In response to TMS control signals and TCK clock signals, the TAP controller selects either the instruction register TIR for entry of an instruction code from the TDI pin, or selects a test data register TDR for entry of data signals from the TDI pin. According to the selected mode of operation, for example a test to be performed or a design specific procedure to be followed, the appropriate instruction code is shifted into the instruction register TIR. The instruction code is decoded by instruction decode register IDR and the TIR selects one or more of the TAP test data registers TDRs required for the selected test or procedure.
The minimum required TDRs include the boundary scan register TDR1 for performing boundary scan testing and the bypass register TDR2 for bypassing data signals and instruction codes to the TDO pin in order to bypass a particular chip for a selected test or other procedure. The TAP may also include design specific TDRs such as TDR4 illustrated in FIG. 1 for performing a customized or design specific procedure as hereafter described. An optional TAP test reset pin or TRST pin may be dedicated for resetting the TAP controller.
The central operating feature of the standard TAP is the boundary scan register TDR1 shown in more detail in FIG. 2. The boundary scan register TDR1 is a shift register of series coupled boundary scan cells BSC. A boundary scan cell BSC is coupled at each pin of the IC device in the system logic path between the respective input or output pin and the IC device internal system logic. Under appropriate program control, data signals may be shifted into position through the boundary scan path of the boundary scan register for example for input to the IC device system logic through the input pins. The processed data signals may be latched at the boundary scan cells adjacent to output pins to be shifted out through the boundary scan path and TDO pin for test analysis. Each boundary scan cell BSC generally incorporates two flip-flops and two multiplexers for accomplishing these boundary scan test objectives. The boundary scan register and boundary scan test principles permit access to all pins of the IC device without physical contact by a "bed of nails" testing apparatus.
A more detailed fragmentary block diagram of the test access port data registers TDRs is illustrated in FIG. 3. FIG. 3 shows a bank of TDRs including the minimum required boundary scan register TDR1 and bypass register TDR2. An optional test data register is the device identification register TDR3 for coded identification of a device name. Additionally there may be a plurality of specialized design specific TAP data registers TDR4, TDR5 and TDRN etc. for design specific tests or procedures.
A state diagram showing the operation of the TAP controller for a standardized test access port is illustrated in FIG. 4. From the Run Test/Idle condition, the TAP controller selects either the TAP test instruction register TIR or one of the TAP test data registers TDRs for shifting respective instruction codes or data signals into and from the captured register TDRN between the TDI and TDO pins. Further background information and detailed instruction on the construction and operation of standardized test access ports are found in the following references: IEEE STANDARD TEST ACCESS PORT AND BOUNDARY SCAN ARCHITECTURE, Test Technology Technical Committee of the IEEE Computer Society, Institute of Electrical and Electronics Engineers, Inc., 345 East 47th Street, New York, N.Y. 10017 U.S.A. (May 21, 1990) (IEEE Standard 1149.1-1990); Colin M. Maunder and Rodham E. Tulloss, THE TEST ACCESS PORT AND BOUNDARY SCAN ARCHITECTURE, IEEE Computer Society Press Tutorial, IEEE Computer Society Press, 10662 Los Vaqueros Circle, P.O. Box 3014, Los Alamitos, Calif. 90720-1264 (IEEE 1990); John Andrews, "IEEE Standard Boundary Scan 1149.1", National Semiconductor Corporation, 333 Western Avenue, South Portland, Me. 04106, WESCON, San Francisco, 1991.
As noted by Maunder and Tulloss, the design specific TAP test data registers TDRs can be part of the on-chip system logic or the test logic and can have both system and test functions. The dedicated test access port pins afford convenient access to the chip for example from a portable computer at an external location for testing or otherwise servicing the IC device in situ in its operating circuit board and environment.
According to the terminology adopted in this specification, the reference to "test" components and elements of the TAP is generalized to "TAP" components and elements to encompass both test logic functions and system logic functions for which the TAP might be used. Thus, the standard test data input pin, test data output pin, test mode select pin, test clock pin, test data registers, and test instruction register etc. are referred to herein more generally as TAP data input (TDI) pin, TAP data output (TDO) pin, TAP mode select (TMS) pin, TAP clock (TCK) pin, TAP data registers (TDRs), and TAP instruction register (TIR) etc. This more generalized terminology is appropriate to objects and features of the present invention implementing the TAP components and elements in system logic functions.